Parallax Completes Open Hardware Vision With Open Source CPU 136
First time accepted submitter PotatoHead (12771) writes "This is a big win for Open Hardware Proponents! The Parallax Propeller Microcontroller VERILOG code was released today, and it's complete! Everything you need to run Open Code on an Open CPU design. This matters because you can now build a device that is open hardware, open code all the way down to the CPU level! Either use a product CPU, and have access to its source code to understand what and how it does things, or load that CPU onto a suitable FPGA and modify it or combine it with your design."
Limited utility. (Score:5, Insightful)
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I'm guessing those who don't trust market CPU's due to backdoor fears will enjoy this.
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As customization reaches lower and lower levels, it becomes increasingly difficult to meaningfully compromise it. Probably the only way to meaningfully compromise an FPGA is to autodetect an internet connectin, and stream out to it everything you receive, possibly only on receiving a particular activation signal. That would be reasonably easy to detect, and even THAT compromise wouldn't be easy, but FPGAs don't have any memory capacity, so they can't accumulate and wait to be polled.
Re:What about the FPGA? (Score:4, Informative)
As customization reaches lower and lower levels, it becomes increasingly difficult to meaningfully compromise it. Probably the only way to meaningfully compromise an FPGA is to autodetect an internet connectin, and stream out to it everything you receive, possibly only on receiving a particular activation signal.
The "FP" in "FPGA" stands for "Field Programmable"; it's possible to compromise in the field, in a rather meaningful way.
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True, but it would take some sort of hardware port to access the programming in the device and be capable of performing that sort of extremely low-level programming to rewrite the chip. I agree with you that it isn't impossible, but to be able to not just detect to also explicitly exploit that vector from much higher level protocols would be very tricky.
This sort of remote reworking of a FPGA was done with the Spirit & Opportunity rovers that are currently on Mars, where NASA (specifically the Jet Prop
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If you can do that on Mars, having a home desktop computer reload new firmware as some sort of malware is trivial by comparison.
Except... NASA specifically designed that functionality into the system.
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I currently have a network router that has similar capabilities. If you can download some firmware and flash it into a device for an update, some malware can certainly do the same thing without your permission.
If on the other hand you need a serial cable of some sort that as a completely separate port for updating the firmware that is code-wise unaddressable from the CPU, it is much harder to do that kind of update. It doesn't stop a co-worker from pulling a prank or somebody with physical access to the c
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No-one with brains or a budget is going to use a 15-20,000 gate FGA to do a job that a 10,000 gate chip can do.
If you need lots of pins on an FPGA, you pretty much have to get one with lots of gates, even if you don't need them all.
Other requirements can also dictate the part you choose.
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Depends on 'compromise.' It's not always about getting data out.
Compromise could mean 'upon detecting this sequence of bytes, suspend your packet filtering for ten seconds so we can sneak our exploit through the firewall.' Or 'upon this sequence of bytes, switch the random number generator off and start using the pre-stored crypto key for new conversations so we can intercept them.'
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FPGAs don't have any memory capacity? They absolutely do -- SRAM, Flash, whatever you're looking for. Some models can even self-modify their own configurations. Imagine a virus that can not only affect your OS, but actually re-wire the CPU in your computer. There are plenty of ways to compromise an FPGA both in terms of stealing the bit configuration or in terms of hiding malicious "code" inside the unused portion of the FPGA's fabric. The manufacturer could easily do this in cahoots with the NSA, or a high
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Something simple like a killswitch would still be possible.
but obvious which is not something you want in a secret backdoor.
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not really, until you can 3-d print it yourself and then verify with an xray will security be verified.
right now only governments and corporations are really able to build their own fabs and thus be 100% certain no backdoors are installed. 3d printing breakthroughs will take that fab and make it a expensive prototype box which can create copies of itself for material prices, as well as make devices such as routers/firewalls etc. leading to cheap devices that can make secure open hardware for defending the w
Reflections on Trusting Trust; Simplicity & Fo (Score:3)
"not really, until you can 3-d print it yourself and then verify with an xray will security be verified."
What if both your 3D printer and X-Ray data analysis software are compromised? See also:
"Reflections on Trusting Trust" by Ken Thompson
http://cm.bell-labs.com/who/ke... [bell-labs.com]
"The final step is represented in Figure 7. This simply adds a second Trojan horse to the one that already exists. The second pattern is aimed at the C compiler. The replacement code is a Stage I self-reproducing program tha
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You're talking about electrical engineering. This is not that.
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You're talking about electrical engineering. This is not that.
From what exposure I've had with HDL, it's a language for electrical engineering. It's different from normal electrical engineering but it's even more different from normal programming.
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Sure, but it is a big bonus for people who need a few custom periherals and a nice, open, stable controller with a good toolchain.
Video processing? Audio processing? Driving oodles of servos? Driving oodles of Neopixels? Does your design need really tight feedback loops (e.g. high speed power control)?
GPLv3 in hardware? (Score:3)
Well, apparently the license to everything is GPLv3, which could cause problems for those wanting to combine it with peripherals of other projects into one FPGA.
Or even if you decide you really want to make lots of them and make an ASIC out of it - how do you apply the GPLv3 to that since you can't really "rebuild" the ASIC...
Also, the tools they have are open-source too, under GPLv3. But since they're the toolchain, I don't think they include the output exemption, which would mean that not only is the proc
"Now"? (Score:2, Informative)
Sort of like OpenRISC [wikipedia.org]? Except, later and worse?
Re: "Now"? (Score:2)
Opensparc delivered a gpl verilog several years ago.
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Open FPGA? (Score:2)
Is there an open-source FPGA design/implementation that you can run this on? Otherwise it's not really open-hardware all the way down, is it..
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I'm not sure there is any toolchain for synthesizing RTL for either FPGAs or silicon that is open source. That's a big project unto itself.
There are a few open source simulators though, so in a sense you can "run" their design under say, Icarus (http://iverilog.icarus.com/). Still, you have to run on proprietary hardware somewhere.
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I use synthesisers and place and route tools, the FPGA manufacturers seem to assume when we want a user friendly tool chain it means we want a graphical tool. So they make very crappy tools. For the record, we want good quality (no crashing, sensible error messages (not "unknown error")) command line tools, like how normal compilers work.
The only reason there are no open source synthesisers and place&route tools is because the specification of the silicon is unavailable.
Specification would be; the forma
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Likewise, it's my understanding that most digital hardware is written in Verilog, not VHDL.
It's a bit different in the FPGA world, and in Europe, but AFAIK, in US chip development, Verilog reigns supreme.
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Only if by "reigns supreme" you mean "is used more" :)
I've gone back and forth between Verilog and VHDL depending on the company I am at throughout my career. Verilog is used more often, but it is absolutely horrible. I know people find the strict typing of VHDL painful, but it really does save a lot of time later during verification. I think people would be surprised at how much VHDL is still used. A large part of Qualcomm uses it still for modem chips and for mobile SOCs.
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Seriously? You have my condolences for using VHDL. You have my deepest sympathy. Second, why the glacial pace? SystemVerilog is supported by all major sim makers (at least to the extent needed to support UVM). Even synthesis tools are starting to support the SystemVerilog constructs tha
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So they make very crappy tools. For the record, we want good quality (no crashing, sensible error messages (not "unknown error")) command line tools, like how normal compilers work.
I have here a log file containing the output from a command-line build of our CPU using the Altera tools. This file is 10460 lines long. The relevant information it contains can be summarised as: No errors, passed timing.
Occasionally, we've had serious issues reported (the reset line on the ethernet MAC wasn't connected, so ended up being set high, which cost us over a week of time debugging the driver and trying to discover why the FIFOs weren't behaving correctly), but they're hidden in so much noise t
here it is (Score:2)
Here's an open FPGA design:
Put a buttload of OR gates in parallel.
Follow them with a buttload of AND gates
There just isn't that much design in a basic FPGA to open up, not that I can see.
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Re:here it is (Score:4, Interesting)
Here's an open FPGA design:
Put a buttload of OR gates in parallel.
Follow them with a buttload of AND gates
There just isn't that much design in a basic FPGA to open up, not that I can see.
Said the blind man.. What you describe is the end user description of a PAL. FPGA's are completely different and PALs are not actually designed that way either. It is just the end user description, much like knowing the x86 instruction set doesn't mean you know how to design a modern x86 processor.
An Altera or Xillinx FPGA is predominately a sea of small SRAM's but there are also many many muxes, complicated interconnects, configurable special function blocks (like multiply/accumulators, IO cells, and Ethernet interfaces). There is also a great deal of logic just to efficiently move configuration bitstreams into the chip. The complexity per unit area is less than a typical ASIC, which makes FPGA's good subjects for bringing up on new process flows but it is definitely not trivial work. Much is low level and structural rather than logical but that doesn't make it easy.
That said, an open FPGA design would be pretty useless. The hardest part is that low level process dependent optimization and that is just not repeatable without an army of engineers, expensive closed source tools, and access to bleeding edge foundries.
What people want, though, isn't to be able to make their own FPGA's. They just want an FPGA that is fully documented. Xilinx and Altera like to keep certain details secret. You have to use their tools because they won't tell you want you need to write your own and, even if you figure it out, they will sue you.
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If the premise is that you don't trust closed hardware or software, then you cannot establish trust by using any closed hardware or software.
If you have an open FPGA you'll need to program it with an open design using an open tool running in an open environment on open hardware.
Unless you've built your CPU, memory, etc. by hand from open transistors and shit, you can't really trust it.
And where are you getting your open electrons from?
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Can you give one example of Open Source Hardware that is "open hardware all the way down"?
If I could make an "Open Source Hardware" design using the actual propeller chip, then sure this makes that design "even more open", and so is a good thing IMO.
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One example of some hardware that is really trying to be "open hardware all the way down" is RepRap. While not completely successful, the goal of the project is to eventually have the hardware build itself. As an open source project, if they are successful, will be quite an accomplishment. Fab@Home is another very similar project with similar goals and an open source hardware implementation. I'm personally partial to Fab@Home, but they are both worthy projects in their own right.
The Open Cores Project a
Performance? (Score:2)
I wonder how this CPU performs? Does it compare to anything I'd care about, or is it more akin to something I'd build a wifi router out of?
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Re:Performance? (Score:5, Informative)
I wonder how this CPU performs? Does it compare to anything I'd care about ...?
The Parallax Propeller CPU [wikipedia.org] is mainly used for hard realtime applications. It has eight 32-bit cores (called "cogs"), each with 2k of dedicated memory, and 32k or shared memory. Each cog runs at 20 MIPS. That is not nearly enough speed or memory for any sort of general computing, but is enough for control loops in embedded systems. The most interesting thing about the PP, is that the general design philosophy is to use a separate core for each task, thus completely eliminating the need for interrupts. So real time latency is drastically reduced.
So how important is any of this? Well, the PP is not very popular, to say the least, and I have never seen one used outside of a hobby project. That is probably why they figure they have nothing to lose by opening it up.
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Hey now...
There's plenty of things you can do with 32k of memory, like going to the moon or playing pong! (Nothing in between)
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The best use of 32k (and approx 0.2 MIPS) I've ever seen is Exile [wikipedia.org]. The map data alone would have been bigger than 32k if it wasn't mostly procedurally generated, and it had a physics engine and particle effects. On one more limited platform (the Acorn Electron) game data had to be visible onscreen around the playing area because memory was so tight. There was nothing left for any kind of HUD, so information (like weapon power remaining) had to be communicated to the player by sound. If you wanted to save yo
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And not a single person got the reference.
So sad...
I recommend googling "Every OS sucks" by Three Dead Trolls in a Baggie
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The most interesting thing about the PP, is that the general design philosophy is to use a separate core for each task, thus completely eliminating the need for interrupts. So real time latency is drastically reduced.
So how important is any of this? Well, the PP is not very popular, to say the least, and I have never seen one used outside of a hobby project. That is probably why they figure they have nothing to lose by opening it up.
Yeah, because to those of us who've done microcontroller development the lack of interrupts just no sells the whole thing, plus it's not like polling is any less complex. Here's an example:
The system is running on battery power, and you want it to use minimal energy. In normal design, you have the chip sleep while waiting for an event that only happens occasionally. (In this context anything under 1kHz can probably be counted as occasionally. Without interupts this thing has to stay awake and have at le
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The clock rate is software programmable - as a fraction of the crystal used. So you can run it at 12 MHz. And then there's a WAITCNT instruction that effectively sleeps till a programmable counter reaches zero. So you can put all the cogs to sleep except one, and only wake the remaining one up as infrequently as you need to poll.
Still not as power efficient for some device that's waiting a long time between events and is running from battery. But a hell of a lot of devices are not that.
And for sure it's far
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In the absence of interrupts, the average latency for responding to an input is one half the sampling time
In hard realtime, nobody gives a crap about average latency. All that matters is the maximum latency. If your timing requirements are flexible, then it is not hard realtime.
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"I wonder how this CPU performs? Does it compare to anything I'd care about, or is it more akin to something I'd build a wifi router out of?"
The Propeller is an interesting beast. It has eight 32-bit cores they call cogs and a hub that ties them all together and gives each of them round-robin access to the 32K of hub RAM. Each core itself only has 2K of RAM it can access, so any assembly program has to fit in this small space.
Most the the time, you don't write assembly code (unless you need the speed), but
Why is this important? (Score:4, Insightful)
Aside from absolutists positions like Stallman's, why is it important to have OS hardware? Why AMD64, Intel x86, or ARM is not good enough?
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because the manufacturers have a monopoly on the security, support and further development of the hardware. We cant make improvements or audit it
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The baseband is not an hardware-ASIC, but runs completely in software, on a general purpose CPU. And the biggest problem is missing legislation to allow for open source mobile basebands.
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Actually, knowing the state of security in cellular networks - especially old 2G and availability of "downgrade to 2G" techniques for newer ones - despite of being strong FLOSS and OH supporter I'm kinda glad that any tech-curious kid next door can't easily play with baseband in his mobile phone.
Sadly, there's also kind of people that won't care that it's illegal and with enough motivation will get all needed hardware, so we're not really protected either way.
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There is the OpenBTS [openbts.org] software & equipment if you want to seriously get into hacking cell phone networks. The authors of that software have even used it for setting up a cell phone network at the Burning Man festivals. They chose this venue in part because being in the middle of nowhere that the Burning Man stuff happens also was unlicensed to commercial cell phone providers, thus they could get experimental FCC licenses for their project and not interfere with existing networks.
In theory, somebody cou
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There're also OpenBSC [osmocom.org] and OsmocomBB [osmocom.org]. However, even with all these projects there's still a pretty steep barrier to enter, which would disappear if open basebands in mobile phones would somehow become common.
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depends on what's important to you.
the more that people use open source code, the more popular that app/widget/whatzit becomes, the more people will want to contribute to that code.
also the more good code there is, the more good code there is to draw from. it seems like a pretty big waste of human potential to keep re inventing the wheel, when if there was a good open source wheel, everyone could use it.
this clearly isn't as good as closed source offerings, but it leans towards good principals.
i for one wou
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I thought the same thing after watching: http://youtu.be/urglg3WimHA [youtu.be]
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TFS misses the point entirely. This isn't a CPU at all, it is a microcontroller. A CUP forms part of a computer system, where as a microcontroller is self contained with its own small memory and peripherals (serial ports, analogue to digital converters, timers etc.)
The Propeller is an interesting microcontroller because it has 8 parallel 32 bit RISC cores. That makes it suitable for some rather unusual tasks that most other micros would need to be paired or quadrupled up for. There is some rather nice libra
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1) You're not reliant on closed hardware vendors to provide drivers for your operating system.
2) You don't have to trust that your hardware vendor isn't reporting your every move to your fascist government.
3) You don't have to worry about your hardware vendor's interests diverging from your own, and stranding you.
There are many more, but I don't have time to post them.
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You write this response as if Windows XP has no market share at all, and that somehow software written for XP won't run on any newer operating systems or computers.
We aren't talking about something written in floating-point BASIC running on ProDOS 1.0 Surprisingly, emulators to run even that software exist on modern computers, so even that can be used.
This is great (Score:3)
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Please explain how the Propeller blows away a Cortex M3 with 96k RAM running at 84MHz with a bunch of hardware peripherals
http://arduino.cc/en/Main/Ardu... [arduino.cc]
Hardware "Vision"?? (Score:2)
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Intimacy... (Score:2)
...and anyone who isn't intimately familiar with microprocessor design, along with every other step of code along the way will still have to trust someone along the chain.
while nice... (Score:1)
Its a real nice gesture on their part and kudos to them, but I dont see this being a huge deal in the long run. I really do not see people that need to use a propeller in their product ( are there any ? ) wanting to go to a more expensive and slower FPGA ( or even a custom ASIC )..
I could be wrong...
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Well, I can see a use for this. If you HAVE an existing FPGA, you could throw a processor on there for free. Some FPGAs have a CPU built-in (such as an ARM), but those parts cost more. With this, if you need some processor, this is not a bad choice. You could go for something like an 8051, but more options are nice to have. This also apparently has a nice software chain (compilers, interpreters, etc.).
If you really need a well-supported embedded soft processor, your choices are OpenRISC, 8051, Z80, 650
Kind of small? (Score:2)
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It's very basic.
There are no hardware peripherals bar a counter and it doesn't even have hardware multiplication
What's the difference? (Score:2)
The site suggests that this can run on the DE0-Nano Cyclone FPGA Board for $90 or the Altera DE2-115 FPGA Development Board for $600. As someone who doesn't know anything about this type of computing... can anyone explain what the difference is between the two?
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Approximately $510 difference between the two.
This is Fantastic! (Score:2)
QR story (Score:1)
truyen phat giao (Score:1)