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Parallax Completes Open Hardware Vision With Open Source CPU 136

First time accepted submitter PotatoHead (12771) writes "This is a big win for Open Hardware Proponents! The Parallax Propeller Microcontroller VERILOG code was released today, and it's complete! Everything you need to run Open Code on an Open CPU design. This matters because you can now build a device that is open hardware, open code all the way down to the CPU level! Either use a product CPU, and have access to its source code to understand what and how it does things, or load that CPU onto a suitable FPGA and modify it or combine it with your design."
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Parallax Completes Open Hardware Vision With Open Source CPU

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  • Re:Limited utility. (Score:2, Interesting)

    by Anonymous Coward on Thursday August 07, 2014 @03:10PM (#47625213)

    I'm guessing those who don't trust market CPU's due to backdoor fears will enjoy this.

  • Re:here it is (Score:4, Interesting)

    by erice ( 13380 ) on Thursday August 07, 2014 @03:51PM (#47625541) Homepage

    Here's an open FPGA design:
    Put a buttload of OR gates in parallel.
    Follow them with a buttload of AND gates

    There just isn't that much design in a basic FPGA to open up, not that I can see.

    Said the blind man.. What you describe is the end user description of a PAL. FPGA's are completely different and PALs are not actually designed that way either. It is just the end user description, much like knowing the x86 instruction set doesn't mean you know how to design a modern x86 processor.

    An Altera or Xillinx FPGA is predominately a sea of small SRAM's but there are also many many muxes, complicated interconnects, configurable special function blocks (like multiply/accumulators, IO cells, and Ethernet interfaces). There is also a great deal of logic just to efficiently move configuration bitstreams into the chip. The complexity per unit area is less than a typical ASIC, which makes FPGA's good subjects for bringing up on new process flows but it is definitely not trivial work. Much is low level and structural rather than logical but that doesn't make it easy.

    That said, an open FPGA design would be pretty useless. The hardest part is that low level process dependent optimization and that is just not repeatable without an army of engineers, expensive closed source tools, and access to bleeding edge foundries.

    What people want, though, isn't to be able to make their own FPGA's. They just want an FPGA that is fully documented. Xilinx and Altera like to keep certain details secret. You have to use their tools because they won't tell you want you need to write your own and, even if you figure it out, they will sue you.

To avoid criticism, do nothing, say nothing, be nothing. -- Elbert Hubbard