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Parallax Completes Open Hardware Vision With Open Source CPU 136

Posted by timothy
from the this-case-is-totally-proprietary dept.
First time accepted submitter PotatoHead (12771) writes "This is a big win for Open Hardware Proponents! The Parallax Propeller Microcontroller VERILOG code was released today, and it's complete! Everything you need to run Open Code on an Open CPU design. This matters because you can now build a device that is open hardware, open code all the way down to the CPU level! Either use a product CPU, and have access to its source code to understand what and how it does things, or load that CPU onto a suitable FPGA and modify it or combine it with your design."
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Parallax Completes Open Hardware Vision With Open Source CPU

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  • Limited utility. (Score:5, Insightful)

    by Dzimas (547818) on Thursday August 07, 2014 @03:04PM (#47625151)
    I run a company that releases all its hardware designs and am a huge proponent of OSHW. This gesture has limited utility simply because the people who use MCUs in designs aren't typically interested in delving into the minutiae of how the processor that runs the system is built. They're more interested in open source circuits which have real-world applications -- a low pass filter for smoothing PWM signals, a nice clean USB power supply, and so on.
    • Re: (Score:2, Interesting)

      by Anonymous Coward

      I'm guessing those who don't trust market CPU's due to backdoor fears will enjoy this.

      • Would it be easier to just use off the shelf items to build your data center and them spend money building an open source thing that sniffs all the packets looking for suspicious crap? I'm asking because I'm not sure it'd be easy to automate identification of "suspicious crap" in the outgoing data.
      • by kesuki (321456)

        not really, until you can 3-d print it yourself and then verify with an xray will security be verified.

        right now only governments and corporations are really able to build their own fabs and thus be 100% certain no backdoors are installed. 3d printing breakthroughs will take that fab and make it a expensive prototype box which can create copies of itself for material prices, as well as make devices such as routers/firewalls etc. leading to cheap devices that can make secure open hardware for defending the w

        • "not really, until you can 3-d print it yourself and then verify with an xray will security be verified."

          What if both your 3D printer and X-Ray data analysis software are compromised? See also:
          "Reflections on Trusting Trust" by Ken Thompson
          http://cm.bell-labs.com/who/ke... [bell-labs.com]
          "The final step is represented in Figure 7. This simply adds a second Trojan horse to the one that already exists. The second pattern is aimed at the C compiler. The replacement code is a Stage I self-reproducing program tha

    • by Gothmolly (148874)

      You're talking about electrical engineering. This is not that.

      • by maligor (100107)

        You're talking about electrical engineering. This is not that.

        From what exposure I've had with HDL, it's a language for electrical engineering. It's different from normal electrical engineering but it's even more different from normal programming.

    • Sure, but it is a big bonus for people who need a few custom periherals and a nice, open, stable controller with a good toolchain.

      Video processing? Audio processing? Driving oodles of servos? Driving oodles of Neopixels? Does your design need really tight feedback loops (e.g. high speed power control)?

    • Well, apparently the license to everything is GPLv3, which could cause problems for those wanting to combine it with peripherals of other projects into one FPGA.

      Or even if you decide you really want to make lots of them and make an ASIC out of it - how do you apply the GPLv3 to that since you can't really "rebuild" the ASIC...

      Also, the tools they have are open-source too, under GPLv3. But since they're the toolchain, I don't think they include the output exemption, which would mean that not only is the proc

  • "Now"? (Score:2, Informative)

    by Anonymous Coward

    This matters because you can now build a device that is open hardware, open code all the way down to the CPU level!

    Sort of like OpenRISC [wikipedia.org]? Except, later and worse?

    • Opensparc delivered a gpl verilog several years ago.

  • Is there an open-source FPGA design/implementation that you can run this on? Otherwise it's not really open-hardware all the way down, is it..

    • I'm not sure there is any toolchain for synthesizing RTL for either FPGAs or silicon that is open source. That's a big project unto itself.

      There are a few open source simulators though, so in a sense you can "run" their design under say, Icarus (http://iverilog.icarus.com/). Still, you have to run on proprietary hardware somewhere.

      • by Anonymous Coward

        I use synthesisers and place and route tools, the FPGA manufacturers seem to assume when we want a user friendly tool chain it means we want a graphical tool. So they make very crappy tools. For the record, we want good quality (no crashing, sensible error messages (not "unknown error")) command line tools, like how normal compilers work.

        The only reason there are no open source synthesisers and place&route tools is because the specification of the silicon is unavailable.
        Specification would be; the forma

        • by pem (1013437)
          Actual software developers write in C, not Ada.

          Likewise, it's my understanding that most digital hardware is written in Verilog, not VHDL.

          It's a bit different in the FPGA world, and in Europe, but AFAIK, in US chip development, Verilog reigns supreme.

          • by SparkEE (954461)

            Only if by "reigns supreme" you mean "is used more" :)

            I've gone back and forth between Verilog and VHDL depending on the company I am at throughout my career. Verilog is used more often, but it is absolutely horrible. I know people find the strict typing of VHDL painful, but it really does save a lot of time later during verification. I think people would be surprised at how much VHDL is still used. A large part of Qualcomm uses it still for modem chips and for mobile SOCs.

        • by harrkev (623093)

          A few years ago we finally started to use VHDL '93 at the moment we expecting to be able to use VHDL2008 in 2028 and this is not a joke, that date is realistic based on historic glacial movement of the hardware industry.

          Seriously? You have my condolences for using VHDL. You have my deepest sympathy. Second, why the glacial pace? SystemVerilog is supported by all major sim makers (at least to the extent needed to support UVM). Even synthesis tools are starting to support the SystemVerilog constructs tha

        • So they make very crappy tools. For the record, we want good quality (no crashing, sensible error messages (not "unknown error")) command line tools, like how normal compilers work.

          I have here a log file containing the output from a command-line build of our CPU using the Altera tools. This file is 10460 lines long. The relevant information it contains can be summarised as: No errors, passed timing.

          Occasionally, we've had serious issues reported (the reset line on the ethernet MAC wasn't connected, so ended up being set high, which cost us over a week of time debugging the driver and trying to discover why the FIFOs weren't behaving correctly), but they're hidden in so much noise t

    • Here's an open FPGA design:
      Put a buttload of OR gates in parallel.
      Follow them with a buttload of AND gates

      There just isn't that much design in a basic FPGA to open up, not that I can see.

      • Actually the AND gates come first, and are followed by OR gates. Then we can have some loopback connections to the same array. But that describes only one macrocell. The algorithms to create efficient (good performance and efficient use of cells) routing between the areas is part of the secret spice.
      • Re:here it is (Score:4, Interesting)

        by erice (13380) on Thursday August 07, 2014 @03:51PM (#47625541) Homepage

        Here's an open FPGA design:
        Put a buttload of OR gates in parallel.
        Follow them with a buttload of AND gates

        There just isn't that much design in a basic FPGA to open up, not that I can see.

        Said the blind man.. What you describe is the end user description of a PAL. FPGA's are completely different and PALs are not actually designed that way either. It is just the end user description, much like knowing the x86 instruction set doesn't mean you know how to design a modern x86 processor.

        An Altera or Xillinx FPGA is predominately a sea of small SRAM's but there are also many many muxes, complicated interconnects, configurable special function blocks (like multiply/accumulators, IO cells, and Ethernet interfaces). There is also a great deal of logic just to efficiently move configuration bitstreams into the chip. The complexity per unit area is less than a typical ASIC, which makes FPGA's good subjects for bringing up on new process flows but it is definitely not trivial work. Much is low level and structural rather than logical but that doesn't make it easy.

        That said, an open FPGA design would be pretty useless. The hardest part is that low level process dependent optimization and that is just not repeatable without an army of engineers, expensive closed source tools, and access to bleeding edge foundries.

        What people want, though, isn't to be able to make their own FPGA's. They just want an FPGA that is fully documented. Xilinx and Altera like to keep certain details secret. You have to use their tools because they won't tell you want you need to write your own and, even if you figure it out, they will sue you.

    • If the premise is that you don't trust closed hardware or software, then you cannot establish trust by using any closed hardware or software.
      If you have an open FPGA you'll need to program it with an open design using an open tool running in an open environment on open hardware.
      Unless you've built your CPU, memory, etc. by hand from open transistors and shit, you can't really trust it.
      And where are you getting your open electrons from?

    • Can you give one example of Open Source Hardware that is "open hardware all the way down"?

      If I could make an "Open Source Hardware" design using the actual propeller chip, then sure this makes that design "even more open", and so is a good thing IMO.

      • by Teancum (67324)

        One example of some hardware that is really trying to be "open hardware all the way down" is RepRap. While not completely successful, the goal of the project is to eventually have the hardware build itself. As an open source project, if they are successful, will be quite an accomplishment. Fab@Home is another very similar project with similar goals and an open source hardware implementation. I'm personally partial to Fab@Home, but they are both worthy projects in their own right.

        The Open Cores Project a

  • I wonder how this CPU performs? Does it compare to anything I'd care about, or is it more akin to something I'd build a wifi router out of?

    • It's an eight core microcontroller and, based off the stats on wikipedia, each core seems to have similar performance to an ATmega2560.
    • Re:Performance? (Score:5, Informative)

      by ShanghaiBill (739463) on Thursday August 07, 2014 @03:44PM (#47625481)

      I wonder how this CPU performs? Does it compare to anything I'd care about ...?

      The Parallax Propeller CPU [wikipedia.org] is mainly used for hard realtime applications. It has eight 32-bit cores (called "cogs"), each with 2k of dedicated memory, and 32k or shared memory. Each cog runs at 20 MIPS. That is not nearly enough speed or memory for any sort of general computing, but is enough for control loops in embedded systems. The most interesting thing about the PP, is that the general design philosophy is to use a separate core for each task, thus completely eliminating the need for interrupts. So real time latency is drastically reduced.

      So how important is any of this? Well, the PP is not very popular, to say the least, and I have never seen one used outside of a hobby project. That is probably why they figure they have nothing to lose by opening it up.

      • Hey now...

        There's plenty of things you can do with 32k of memory, like going to the moon or playing pong! (Nothing in between)

        • The best use of 32k (and approx 0.2 MIPS) I've ever seen is Exile [wikipedia.org]. The map data alone would have been bigger than 32k if it wasn't mostly procedurally generated, and it had a physics engine and particle effects. On one more limited platform (the Acorn Electron) game data had to be visible onscreen around the playing area because memory was so tight. There was nothing left for any kind of HUD, so information (like weapon power remaining) had to be communicated to the player by sound. If you wanted to save yo

        • And not a single person got the reference.

          So sad...

          I recommend googling "Every OS sucks" by Three Dead Trolls in a Baggie

      • The most interesting thing about the PP, is that the general design philosophy is to use a separate core for each task, thus completely eliminating the need for interrupts. So real time latency is drastically reduced.

        So how important is any of this? Well, the PP is not very popular, to say the least, and I have never seen one used outside of a hobby project. That is probably why they figure they have nothing to lose by opening it up.

        Yeah, because to those of us who've done microcontroller development the lack of interrupts just no sells the whole thing, plus it's not like polling is any less complex. Here's an example:

        The system is running on battery power, and you want it to use minimal energy. In normal design, you have the chip sleep while waiting for an event that only happens occasionally. (In this context anything under 1kHz can probably be counted as occasionally. Without interupts this thing has to stay awake and have at le

        • The clock rate is software programmable - as a fraction of the crystal used. So you can run it at 12 MHz. And then there's a WAITCNT instruction that effectively sleeps till a programmable counter reaches zero. So you can put all the cogs to sleep except one, and only wake the remaining one up as infrequently as you need to poll.

          Still not as power efficient for some device that's waiting a long time between events and is running from battery. But a hell of a lot of devices are not that.

          And for sure it's far

    • by Jerrry (43027)

      "I wonder how this CPU performs? Does it compare to anything I'd care about, or is it more akin to something I'd build a wifi router out of?"

      The Propeller is an interesting beast. It has eight 32-bit cores they call cogs and a hub that ties them all together and gives each of them round-robin access to the 32K of hub RAM. Each core itself only has 2K of RAM it can access, so any assembly program has to fit in this small space.

      Most the the time, you don't write assembly code (unless you need the speed), but

  • by sinij (911942) on Thursday August 07, 2014 @03:31PM (#47625379) Journal

    Aside from absolutists positions like Stallman's, why is it important to have OS hardware? Why AMD64, Intel x86, or ARM is not good enough?

    • Re: (Score:2, Informative)

      by Anonymous Coward

      because the manufacturers have a monopoly on the security, support and further development of the hardware. We cant make improvements or audit it

    • by Anonymous Coward

      depends on what's important to you.

      the more that people use open source code, the more popular that app/widget/whatzit becomes, the more people will want to contribute to that code.

      also the more good code there is, the more good code there is to draw from. it seems like a pretty big waste of human potential to keep re inventing the wheel, when if there was a good open source wheel, everyone could use it.

      this clearly isn't as good as closed source offerings, but it leans towards good principals.

      i for one wou

    • by Type44Q (1233630)
      Because backdoors.
    • by AmiMoJo (196126) *

      TFS misses the point entirely. This isn't a CPU at all, it is a microcontroller. A CUP forms part of a computer system, where as a microcontroller is self contained with its own small memory and peripherals (serial ports, analogue to digital converters, timers etc.)

      The Propeller is an interesting microcontroller because it has 8 parallel 32 bit RISC cores. That makes it suitable for some rather unusual tasks that most other micros would need to be paired or quadrupled up for. There is some rather nice libra

    • 1) You're not reliant on closed hardware vendors to provide drivers for your operating system.
      2) You don't have to trust that your hardware vendor isn't reporting your every move to your fascist government.
      3) You don't have to worry about your hardware vendor's interests diverging from your own, and stranding you.

      There are many more, but I don't have time to post them.

    • The reason that we've open sourced our CPU [bericpu.org] (not the one in TFA) is to promote research. The vast number of papers published in computer architecture conferences and journals evaluate their approach solely on a simulator and hope that there's some relationship between the simulator and reality. While a softcore CPU is not exactly like a real CPU, being able to implement your ideas in an FPGA (and pass timing!) does at least mean that it is possible to implement them in a real CPU, although it doesn't guara
  • by spiritplumber (1944222) on Thursday August 07, 2014 @04:14PM (#47625715)
    the Prop came out before the Arduino and still blows anything in the Arduino family out of the water, except for needing some external parts to do ADC. Can't wait for the Prop 2.
  • For a second there I thought parallax had executed a machine vision sensor system driven by their micro-controller. That would have been so much cooler than this all but empty gesture.
  • ...and anyone who isn't intimately familiar with microprocessor design, along with every other step of code along the way will still have to trust someone along the chain.

  • Its a real nice gesture on their part and kudos to them, but I dont see this being a huge deal in the long run. I really do not see people that need to use a propeller in their product ( are there any ? ) wanting to go to a more expensive and slower FPGA ( or even a custom ASIC )..

    I could be wrong...

    • by harrkev (623093)

      Well, I can see a use for this. If you HAVE an existing FPGA, you could throw a processor on there for free. Some FPGAs have a CPU built-in (such as an ARM), but those parts cost more. With this, if you need some processor, this is not a bad choice. You could go for something like an 8051, but more options are nice to have. This also apparently has a nice software chain (compilers, interpreters, etc.).

      If you really need a well-supported embedded soft processor, your choices are OpenRISC, 8051, Z80, 650

  • Looking at the source code (dismissing blank and comment lines) it seems to be only about 800 lines of Verilog.
    • It's very basic.
      There are no hardware peripherals bar a counter and it doesn't even have hardware multiplication

  • The site suggests that this can run on the DE0-Nano Cyclone FPGA Board for $90 or the Altera DE2-115 FPGA Development Board for $600. As someone who doesn't know anything about this type of computing... can anyone explain what the difference is between the two?

  • I've always liked the PP for its novel approach to a multi-core micro. Opening up the hardware design like this can really grow its application space. Just because you can't imagine a use for this doesn't mean there is no use for it. And these days, FPGAs are making great strides in their accessibility. Verilog is the language of choice for most because of its similiarities with C. VHDL is mostly relegated to defense, because it has its roots in Ada (the syntax is almost identical). If you're into functiona

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