Parallax Completes Open Hardware Vision With Open Source CPU 136
First time accepted submitter PotatoHead (12771) writes "This is a big win for Open Hardware Proponents! The Parallax Propeller Microcontroller VERILOG code was released today, and it's complete! Everything you need to run Open Code on an Open CPU design. This matters because you can now build a device that is open hardware, open code all the way down to the CPU level! Either use a product CPU, and have access to its source code to understand what and how it does things, or load that CPU onto a suitable FPGA and modify it or combine it with your design."
"Now"? (Score:2, Informative)
Sort of like OpenRISC [wikipedia.org]? Except, later and worse?
Re:Why is this important? (Score:2, Informative)
because the manufacturers have a monopoly on the security, support and further development of the hardware. We cant make improvements or audit it
Re:Performance? (Score:5, Informative)
I wonder how this CPU performs? Does it compare to anything I'd care about ...?
The Parallax Propeller CPU [wikipedia.org] is mainly used for hard realtime applications. It has eight 32-bit cores (called "cogs"), each with 2k of dedicated memory, and 32k or shared memory. Each cog runs at 20 MIPS. That is not nearly enough speed or memory for any sort of general computing, but is enough for control loops in embedded systems. The most interesting thing about the PP, is that the general design philosophy is to use a separate core for each task, thus completely eliminating the need for interrupts. So real time latency is drastically reduced.
So how important is any of this? Well, the PP is not very popular, to say the least, and I have never seen one used outside of a hobby project. That is probably why they figure they have nothing to lose by opening it up.
Re:What about the FPGA? (Score:4, Informative)
As customization reaches lower and lower levels, it becomes increasingly difficult to meaningfully compromise it. Probably the only way to meaningfully compromise an FPGA is to autodetect an internet connectin, and stream out to it everything you receive, possibly only on receiving a particular activation signal.
The "FP" in "FPGA" stands for "Field Programmable"; it's possible to compromise in the field, in a rather meaningful way.